Digital-to-analog converters (DACs) play a critical role in transforming information from a digital domain into an analog domain. DACs generally convert an abstract finite precision number (such as a fixed-point binary number) into a physical quantity (such as a voltage or current). The number of output levels for a given DAC generally corresponds to its resolution, which is based on the number of “bits” of a given digital code that defines each output level. A variety of DAC architectures exist, including voltage-mode schemes and current steering schemes.
FIG. 1 illustrates a voltage-mode DAC, generally designated 100. The DAC includes a data input 102 that receives a data word of multiple bits during a bit time and a clock input 104 that receives a clock. Respective supply (VDD) and ground (VSS) reference voltages are provided to the DAC. Switch circuitry (not shown) responds to the clock to generate corresponding outputs that are weighted and summed to create an overall output voltage level corresponding to the input word code, but in the analog domain.
FIG. 2A illustrates one conventional approach in generating the output voltage level for a DAC. The DAC includes respective DAC drivers 2000-200n-1 for processing each “bit” b0-bn-1 of the input word. Each driver includes a first switch SW1 that selectively couples an output resistance ROUT to the supply voltage VDD. A second switch SW2 selectively couples the output resistance to the ground voltage VSS. The switches cooperate to form a push-pull driver. In practice, the switching moments of each switch are individually tuned during manufacture such that both switches are not closed at the same moment, which would create undesirable crow-bar currents. Often, the switches are driven very quickly to also minimize undesirable high-ohmic output states, which distort the output impedance. This “direct” switching approach may be susceptible to data-dependent distortion, such as through inter-symbol interference (ISI) and other errors.
In an effort to improve on the “direct” switching approach, the driver circuitry may be split into two circuits, such as shown in FIG. 2B, at 202 and 204. The split driver circuitry includes a separate output resistance ROUT for each of the sub-drivers. This double load solution dampens any short-circuit current that may occur should both switches be simultaneously closed. However, both loads are typically not exactly equal. Thus, depending on the data, the load may change. Employing a return-to-zero switching protocol minimizes data-dependent switch current in favor of a clock-dependent switching current. However, the dual load approach may still be subject to influences on the output impedance resulting from parasitic capacitances from the split driver circuits. What is needed is a power-efficient method and apparatus to support switching operations for a voltage-mode DAC driver.